1. Field of the Invention
The invention relates to a differential amplifier circuit, and more particularly to a differential amplifier circuit with a high slew rate.
2. Description of the Related Art
FIG. 1 illustrates a conventional differential amplifier circuit capable of reducing current consumption and proposed in U.S. Pat. No. 6,392,485. In FIG. 1, since the conventional differential amplifier circuit has a reduced steady-state current, charging and discharging speeds of the capacitors (C1, C2) are limited, and variations of gate voltages of the transistors (M15, M16) are limited. Thus, a slew rate of the output voltage (Vout) is limited. Therefore, when variations of the gate voltages of the transistors (M15, M16) are detected respectively by the transistors (M18, M19), the transistors (M18, M19) are turned on to provide a temporary-state current such that the capacitors (C1, C2) receive the temporary-state and steady-state currents to raise the charging and discharging speeds, thereby enhancing the slew rate of the output voltage (Vout).
However, when the gate-source voltage or the source-gate voltage of the transistors (M15, M16) in the steady state is greater than a threshold voltage, the transistors (M18, M19) are turned on. As a result, the differential amplifier circuit has an increased steady-state current, thereby increasing power consumption.